The present invention relates to level shifting circuits and in particular to a circuit for converting a binary input signal to a binary output signal wherein the input and output signals have differing high and/or low logic levels.
A logic signal output of a typical emitter-coupled logic (ECL) gate has high and low logic levels of about -0.9 and -1.6 volts, while a logic signal output of a typical transistor-transistor logic (TTL) gate has high and low logic levels of about 4.0 and 0.4 volts. Sometimes it is necessary to convert the output of an ECL gate to a TTL compatible signal, to adapt the output of a TTL circuit to be compatible with an ECL input or to make other such voltage conversions. One common way of converting such signal levels is shown in FIG. 1. An ECL level input signal V.sub.in is applied to a level shifting circuit 10 which produces an output signal applied to the base of an output transistor 12. In response to a high logic level input signal V.sub.in, the level shifting circuit 10 produces an output voltage which is sufficient to turn on transistor 12 which then draws current through a load resistor 14 from a supply voltage V.sub.CC. This pulls down the output signal V.sub.o at the collector of transistor 12. When the input signal V.sub.in is low, level shifting circuit 10 produces an output voltage which is not high enough to turn transistor 12 on and the output signal V.sub.o at the collector of transistor 12 is pulled up to the potential of V.sub.CC. By appropriately choosing the amount of input signal level shift, the value of the load resistor 14, and the supply voltage V.sub.CC, the TTL output signal V.sub.o can be made to vary between 0.4 and 4 volts when the ECL input signal V.sub.in varies between -0.9 and -1.6 volts.
The implementation of the circuit of FIG. 1 usually involves tradeoffs. Zener diodes are commonly utilized for level shifting but sometimes add expense to integrated circuits. Level shifting resistor networks can be used but tend to slow the response of the circuit. Also, due to variation in device parameters, transistor 12 can become saturated when it is turned on, thereby causing excess charge to be stored in inherent circuit capacitance between the base and emitter of transistor 12. This charge must be removed before the transistor can be turned off, and the time required to remove this charge increases the response time of the circuit. Clamping circuits are often provided to limit the fall of collector potential as the output transistor turns on, thereby preventing the output transistor 12 from saturating. Various approaches to clamping output transistors to prevent saturation are described in U.S. patents Nos. 4,415,817 to Fletcher, 3,699,355 to Madrazo et al, 3,676,713 to Wiedmann, and 3,473,047 to Bohn et al. However, clamping often adds to the power dissipation of a device and sometimes increases the amount of capacitance in the switching path which can decrease switching speed.
Feedback circuits have also been utilized to limit the voltage supplied to the base of a load transistor when its collector potential tries to fall below the base voltage. In U.S. Pat. No. 4,055,794 to Ickes et al, an operational amplifier compares the load transistor collector voltage to its base voltage or to a reference voltage, and turns on a feedback transistor when the collector voltage falls too low. The collector of the feedback transistor is coupled to the base of the output transistor and the emitter of the feedback transistor is connected to the emitter of the output transistor. When the feedback transistor turns on it reduces the base voltage of the load transistor to a point where the load transistor is not saturated. However, due to the generally slow response time of a feedback loop utilizing an operational amplifier, the output transistor will saturate before the feedback circuit can reduce the base potential enough to bring the load transistor back out of saturation. This approach is suitable for use in controlling current supplied to large motors wherein fast turnoff of the load transistor is required, but wherein overall switching speed of the circuit is not important and short term saturation of the load transistor is tolerable. However, this approach is not suitable for high speed logic systems implemented in integrated circuit form, since short term saturation of a load transistor in an integrated circuit can cause latchup.